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RE: [DSP-RADIO] DSP radio design

certainly not a daft thought!

check out...... www.qsl.net/amsat-dsp-radio


Simon GM4PLM

-----Original Message-----
From: owner-dsp-radio@qth.net [mailto:owner-dsp-radio@qth.net]On Behalf
Of W Lewis
Sent: 18 January 2001 23:37
To: dsp-radio@qth.net
Subject: [DSP-RADIO] DSP radio design

W Lewis <wiml@hhhh.org>
I've been kicking around thoughts of a "soft" homebrew radio for the past
six months or so and just found this list. I'm gratified to discover that
the ideas I'd come up with are pretty similar to the ones people are
talking about here --- it suggests I might not be completely off my rocker

I thought I'd describe my mental design here to stimulate some discussion.
It differs from what other people have been talking about on a few points,
both because I have slightly different goals, and because I don't really
know what I'm doing. Any comments or criticisms are welcome!

My goal was to come up with a radio design that would be useful for
experimenting with terrestrial, digital, wide-band modes: either
high-data-rate modes, or lower data rate modes using spread spectrum
techniques. Mostly in the 1GHz-and-up bands (starting with the 900MHz ISM
band, I suppose). The cellular industry seems to be talking about soft
radios as a way to "future-proof" their cell sites; I want a "mode-proof"
radio. What started me thinking along these lines was noticing some Maxim
wide-bandwidth balanced mixers and ADCs presumably designed for cell-phone

The radio design falls neatly into three parts:
   1. RF/analogue front end, up to (and including) the A/D and D/A
   2. DSP and control circuitry
   3. Host computer
I'll describe them one at a time.

1. RF/analogue front end. Not being an expert on RF design, I was thinking
of doing a direct conversion from the 1GHz band (with a wideband filter
plus LNA) down to baseband, and feeding the I/Q outputs into a two-channel
ADC such as the AD6600 or Maxim MAX1005.  (The 1005 doesn't have as much
dynamic range, though.) Most of the designs I've seen here have at least
two, sometimes three mixers --- I assume this is to avoid LO feedthrough
into later stages and the resulting intermodulation products? Is this
desirable even if you're not doing weak-signal work? LO leakage might be
even more undesirable in the transmitter...

Anyway, the RF section would also have the GHz-range LO (probably a PLL
running from a clock supplied by the dsp/control board). It could also
contain one of those tiny serial EEPROMs to allow it to be identified by
the DSP board. The EEPROM could contain the board's model number, and
information on which filters are attached to it, etc.

My thought was to have this board be separated from the rest of the
system, connected by ribbon cable (not an card-edge connector), to make it
easier to shield it from all the digital noise. Possibly multiple
frontends could be attached to one DSP board, for diversity, phased-array,
or DF uses.

2. DSP/control board. This would take the raw digital samples from the RF
board and massage them into a bitstream for the host to do something with,
and take a bitstream from the host and compute values to be sent to the
DAC on the RF board.

Here's another place where my design has deviated a bit from the designs
talked about on this list. I was thinking I'd need a bit of random logic
to clock the A/D/D/A, to glue it to the DSP, and so forth, and so I
thought of putting an FPGA (or CPLD) on this board. Once I was thinking in
terms of using an FPGA, lots of other advantages occurred to me:

  1. If the RF module is interfaced through an FPGA, this also makes it
  easier to design multiple swappable RF modules for different bands, or
  to deal with obsoleted parts, without having to redesign the DSP board.

  2. Lots of modulation schemes involve a bit of bit-manipulation (easy in
  HW, harder in SW), followed by a lookup table. This is easy to do in an
  FPGA. (Of course, the lookup table should be followed by a
  digital-domain LPF, probably  --- I haven't thought this out

  3. The samples coming from the RF board are coming quite fast ---
  several Msps, perhaps. (Let's say 12+ Msps, for a nominal 6 MHz signal
  bandwidth.) It'll be hard to find a DSP that can handle that sample
  rate. But it wouldn't be very hard at all to put a bunch of DSP into an
  FPGA. An FPGA, being inherently very parallel, should be able to
  implement lots of filter structures pretty efficiently. The FPGA could
  do the IF filtering, followed by a second mixing stage and possibly
  even the final demodulation of the signal to bitstream form. (teh
  AD6620 wouldn't be needed in this case.) If this is practical, I'm not
  sure that a dedicated DSP would even be needed! Of course, I haven't
  tried fitting all this onto a real-world FPGA --- but there are some
  really huge FPGAs available these days, for not more money than a good

The downside of such heavy use of the FPGA is that FPGA design is a
different art from DSP design. I'm not experienced with either, but DSP
programming is certainly closer to my day job of programming
general-purpose computers than FPGA design is! I've looked through some
books on FPGA design, though, and it doesn't look impossible to learn.

3. The host computer. Since I'm interested in experimenting with data
modes, a stand-alone rig doesn't make as much sense. The easiest ways to
communicate with the host, I think, are ethernet and USB. Ethernet is
simpler, but there are some nicely integrated USB chips out there (I'm
thinking of the Anchor / Cypress EZ-USB line). Firewire is fast, but looks
really difficult to implement, and I don't think async serial has the
necessary bandwidth. If a PC/104 board is used as a host, then the DSP
board could use the ISA bus.

It probably makes sense to have a small supervisory controller on the DSP
board (especially if it's entirely FPGA-based). A PIC or AVR
microcontroller would do nicely. If the board talks USB to the host, then
the 8051 that's built in to the EZ-USB chip could handle this.

I'd like to have as little nonvolatile storage in the system as possible
--- everything should be dowloaded from the host at boot time. This makes
the development/debug cycle easier. :-) Ideally, the only nonvolatile
storage would be ID eeproms on the RF boards. The host computer would have
a disk, of course (maybe a flash disk).

I'm interested in keeping the design as "open" as possible --- the boards
and the FPGA/DSP source code would be open-source; the host computer would
be running Linux or NetBSD. (Of course, if someone wants to use a Windows
or DOS machine as a host, that's fine, but personally I'm interested in
using unixy platforms.)

Wim Lewis / wiml@hhhh.org


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